Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect

ABSTRACT

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

CLAIM OF PRIORITY

This application is a continuation application under 35 U.S.C. 120 ofprior U.S. application Ser. No. 14/949,761, filed Nov. 23, 2015, whichis a continuation application under 35 U.S.C. 120 of prior U.S.application Ser. No. 14/216,891, filed Mar. 17, 2014, issued as U.S.Pat. No. 9,202,779, on Dec. 1, 2015, which is a continuation applicationunder 35 U.S.C. 120 of prior U.S. application Ser. No. 13/897,307, filedMay 17, 2013, issued as U.S. Pat. No. 8,701,071, on Apr. 15, 2014, whichis a divisional application under 35 U.S.C. 121 of prior U.S.application Ser. No. 12/363,705, filed Jan. 30, 2009, issued as U.S.Pat. No. 8,453,094, on May 28, 2013, which claims priority under 35U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/024,980,filed Jan. 31, 2008. The disclosure of each above-identified patentapplication is incorporated herein by reference.

BACKGROUND

FIG. 1 shows a typical CMOS transistor configuration, in accordance withthe prior art. In the example of FIG. 1, a preferred direction for aninterconnect level (metal-1) is parallel to that for gate electrode(gate) wires, as seen for metal-1 wire 105 and gate wire 103. Gate wire103 overlaps a diffusion shape 101, forming a transistor with a sourceor drain (S/D) node that is connected to metal-1 wire 105 by a contact106. Wire 105 requires a non-rectangular shape, i.e., a shape with abend, to allow it to overlap a contact 102 which connects to a gate wire107. FIG. 1 also shows a gate electrode wire 104 that requires a bend tooverlap a gate contact 108, which connects to a metal-1 wire 109.

The typical CMOS transistor configuration of FIG. 1 illustrates a numberof features that may increase manufacturing difficulty. For example,contacts for S/D and gate connections are not aligned, gate and metalwire widths are variable, spacing between wire shapes is variable, wirecenter lines are variably spaced apart, and a ratio of filled tonon-filled space for gate and metal-1 levels is variable. These featuresmay cause parametric and defect yield loss in advanced semiconductorprocesses due to associated lithographic effects, CMP (chemicalmechanical planarization) dishing, and/or other manufacturingimperfections. Therefore, it is of interest to define a semiconductordevice layout methodology that accounts for layout characteristics whichadversely affect manufacturability.

SUMMARY

In one embodiment, a method is disclosed for defining a layout for aportion of a given semiconductor chip level. The method includes anoperation for defining a preferred routing direction for a given chiplevel. The method also includes an operation for identifying eachcontact level related to the given chip level, wherein each contactlevel includes at least one interfacing contact defined to physicallyconnect with a structure corresponding to a layout shape to be placed inthe given chip level. An operation is then performed to define a globalplacement grating (GPG) for the given chip level to include a set ofparallel and evenly spaced virtual lines. At least one virtual line ofthe GPG is positioned to intersect each interfacing contact within eachcontact level related to the given chip level. A determination is thenmade as to whether a perpendicular spacing between adjacent virtuallines of the GPG provides for enforcement of layout shape patternregularity within the given chip level as necessary to ensuremanufacturability of layout shapes within the given chip level. If it isdetermined that the perpendicular spacing between adjacent virtual linesof the GPG is acceptable, the method proceeds with placement of layoutshapes in alignment with the GPG for the given chip level. However, ifit is determined that the perpendicular spacing between adjacent virtuallines of the GPG is not acceptable, the method proceeds with anoperation for adjusting placement of one or more interfacing contactswithin one or more contact levels related to the given chip level. Themethod then reverts back to the operation for defining the GPG for thegiven chip level.

In another embodiment, a method is disclosed for defining a layout for aportion of a given semiconductor chip level. In the method, a GPG isdefined for a given chip level. The GPG is defined by a set of paralleland evenly spaced virtual lines. The method includes identifying allconnection lines within the GPG. A connection line is a virtual line ofthe GPG that is spatially coincident with a virtual line of a relatedcontact level. A subgrating is defined for the given chip level as a setof evenly spaced connection lines, such that a spacing between adjacentconnection lines in the subgrating is at least as large as a minimumspacing required to support a common run length of layout shapes on theadjacent connection lines in the subgrating. Definition of subgratingsis repeated until each connection line within the GPG is associated withat least one subgrating. The method further includes placement of layoutshapes in alignment with the defined subgratings, such that each layoutshape is associated with any one subgrating.

In another embodiment, a method is disclosed for defining a layout for aportion of a given semiconductor chip level. The method includes anoperation for defining a GPG for a given chip level. The GPG is definedby a set of parallel and evenly spaced virtual lines. All connectionlines within the GPG are identified. A connection line is a virtual lineof the GPG that is spatially coincident with a virtual line of a relatedcontact level. The method also includes an operation for defining asubgrating for the given chip level as a set of evenly spaced connectionlines, such that a spacing between adjacent connection lines in thesubgrating is at least as large as a minimum spacing required to supporta common run length of layout shapes on the adjacent connection lines inthe subgrating. The operation for defining the subgrating is repeateduntil each connection line within the GPG is associated with at leastone subgrating. The layout for the given chip level is then partitionedinto a number of subgrating regions. Each subgrating region is definedas a contiguous area within the layout for the given chip level.Subgratings are allocated to the number of subgrating regions such thatonly one subgrating is allocated to any one subgrating region. Themethod further includes an operation for placing functional layoutshapes for the given chip level in alignment to the subgratingsallocated to the subgrating regions. Following placement of thefunctional layout shapes, a non-standard spacing is identified withinthe layout of the given chip level. The method includes an operation forresolving the non-standard spacing so as to ensure manufacturability ofstructures corresponding to the functional layout shapes.

Other aspects and advantages of the invention will become more apparentfrom the following detailed description, taken in conjunction with theaccompanying drawings, illustrating by way of example the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a typical CMOS transistor configuration, in accordance withthe prior art;

FIG. 2 shows a portion of a layout for a given chip level in which a GPGis defined and in which linear layout shapes are placed in alignmentwith the GPG, in accordance with one embodiment of the presentinvention;

FIG. 3A shows an example in which a subgrating pitch results in a ratioof side-to-side spacing to layout shape width that is too large tomaintain sufficient shape density for proper manufacturing;

FIG. 3B shows a modification of the layout of FIG. 3A in which asubresolution shape is used to mitigate the unacceptably largeside-to-side spacing to width ratio, in accordance with one embodimentof the present invention;

FIG. 4 shows an example layout in which a GPG is used to place layoutshapes for gate electrode wires, interconnect wires, diffusion contacts,and gate contacts, in accordance with one embodiment of the presentinvention;

FIG. 5 shows an extension of the exemplary layout of FIG. 4 in which anumber of subgrating regions are defined in various chip levels, inaccordance with one embodiment of the present invention;

FIG. 6 shows an example layout that illustrates subgrating use amongdifferent vertically stacked chip levels, in accordance with oneembodiment of the present invention;

FIG. 7 shows an example layout in which a multi-level orthogonallyrouted connection is used to connect wires in a same chip level thatcannot have a common run length, in accordance with one embodiment ofthe present invention;

FIG. 8 shows another example layout in which a multi-level orthogonallyrouted connection is used to connect wires in a same chip level thatcannot have a common run length, in accordance with one embodiment ofthe present invention;

FIG. 9A shows an example layout that illustrates the occurrence of anon-standard spacing at an interface between adjacent subgratingregions, in accordance with one embodiment of the present invention;

FIG. 9B shows a layout shape stretching technique for mitigating anon-standard spacing introduced at subgrating region borders that lieparallel to the routing direction, in accordance with one embodiment ofthe present invention;

FIG. 10A shows an example layout that illustrates the occurrence of anon-standard spacing at an interface between adjacent subgratingregions, when the layout shape stretching technique of FIG. 9B isblocked, in accordance with one embodiment of the present invention;

FIG. 10B illustrates use of a subresolution shape to mitigate anon-standard spacing at an interface between adjacent subgratingregions, when the layout shape stretching technique of FIG. 9B isblocked, in accordance with one embodiment of the present invention;

FIG. 11 shows an exemplary layout in which a layout shape is stretchedto overlap multiple contacts and/or vias, in accordance with oneembodiment of the present invention;

FIG. 12 shows another example in which layout shapes are stretched tooverlap multiple contacts and/or vias, in accordance with one embodimentof the present invention;

FIG. 13 shows an example in which layout shapes are extended relative toa contact and/or via so as to accommodate design requirements, inaccordance with one embodiment of the present invention;

FIG. 14 shows a flowchart of a method for defining a layout for aportion of a given semiconductor chip level, in accordance with oneembodiment of the present invention;

FIG. 15A shows a flowchart of a method for defining a layout for aportion of a given semiconductor chip level, in accordance with oneembodiment of the present invention;

FIG. 15B shows an expanded view of operation 1509 of FIG. 15A, inaccordance with one embodiment of the present invention;

FIG. 15C shows an extension of the method of FIGS. 15A-15B, inaccordance with various embodiments of the present invention; and

FIG. 16 shows a flowchart of a method for defining a layout for aportion of a given semiconductor chip level, in accordance with oneembodiment of the present invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Itwill be apparent, however, to one skilled in the art that the presentinvention may be practiced without some or all of these specificdetails. In other instances, well known process operations have not beendescribed in detail in order not to unnecessarily obscure the presentinvention.

Within the context of the present invention, a global placement grating(GPG) is defined by a set of parallel and evenly spaced virtual linesextending across a semiconductor chip (“chip” hereafter) level. Theeven, i.e., equal, perpendicular spacing between adjacent virtual linesof a GPG is referred to at the GPG pitch (GPGP). Layout shapes within aportion of a given chip level can be placed in accordance with the GPGof the given chip level. For example, layout shapes within a portion ofa given chip level may be centered upon or in some way indexed tovirtual lines of the GPG of the given chip level. Also, the virtuallines of the GPG of a given chip level are oriented to extend in apreferred routing direction of the given chip level, wherein thepreferred routing direction corresponds to a direction in which layoutshapes are defined to extend.

In one embodiment, the layout shapes placed in accordance with the GPGare defined as linear layout shapes. Each linear layout shape has asubstantially rectangular cross-section when viewed in an as-drawnstate. In one embodiment, the linear layout shape does allow for smalldeviations from the rectangular cross-section. For example, a linearlayout shape may include one or more expanded regions along itsrectangular cross-section length so as to accommodate contact placementsand connections thereto. In another embodiment, strict adherence to asubstantially rectangular cross-section may be specified for the linearlayout shapes. It should be understood that a degree of rectangularityof the linear layout shapes can vary between embodiments, depending onthe requirements for design and layout of a particular embodiment. Inone embodiment, each linear layout shape placed in a portion of a givenchip level is placed such that a length of its substantially rectangularcross-section is parallel with the GPG of the given chip level.Therefore, in this embodiment, the linear layout shapes extend in thepreferred routing direction of the given chip level which is parallel tothe virtual lines of the GPG.

Also, in one embodiment, each linear layout shape is initially placed ina centered manner such that its centerline extending in the preferredrouting direction is substantially centered upon a virtual line of theGPG. It should be understood, however, that following initial placementof a given layout shape in the centered manner, a width of the givenlayout shape may be adjusted, or the given layout shape may be stretchedin its width direction, such that a final version of the given layoutshape is no longer centered upon a virtual line of the GPG.

FIG. 2 shows a portion of a layout for a given chip level in which a GPGis defined and in which linear layout shapes are placed in alignmentwith the GPG, in accordance with one embodiment of the presentinvention. The GPG of FIG. 2 is defined by virtual lines 200-209, withadjacent virtual lines evenly spaced at the GPG pitch (GPGP). Thevirtual lines 200-209 of the GPG extend in the preferred routingdirection of the given chip level. FIG. 2 depicts layout shapes asshaded rectangular shapes. The layout shapes within the portion of thegiven chip level are defined as linear layout shapes and are placed soas to be substantially centered upon a virtual line of the GPG.

FIG. 2 further illustrates concepts of the present invention referred toas subgrating and subgrating regions. A subgrating is defined as a setof evenly spaced GPG lines having a subgrating pitch that is an integermultiple of the GPG pitch. A subgrating region is defined as a layoutarea of a portion of a given chip level within which layout shapes areplaced according to a single subgrating. In one embodiment, a subgratingis defined to accommodate a common run length of layout shapes having aspecified uniform width, wherein the common run length refers toside-by-side existence of layout shapes on adjacent subgrating virtuallines.

FIG. 2 shows by way of example five separate subgrating regions 220-224,where a periphery of each subgrating region 220-224 is delineated bybold solid lines. Each of subgrating regions 220-224 is associated witha particular subgrating. The subgrating within each subgrating region220-224 is delineated by bold dashed lines. The subgratings for each ofsubgrating regions 220 and 224 include each virtual line of the GPG (GPGvirtual lines 200-206 for subgrating region 220, and GPG virtual lines207-209 for subgrating region 224). The subgrating for subgrating region221 includes every other even numbered virtual line of the GPG (GPGvirtual lines 200, 202, 204, 206), such that the correspondingsubgrating pitch is 2*GPGP. The subgrating for subgrating region 222includes every other odd numbered virtual line of the GPG (GPG virtuallines 201, 203, 205, 207, 209), such that the corresponding subgratingpitch is 2*GPGP. The subgrating for subgrating region 223 includes everythird virtual line of the GPG, (GPG virtual lines 201 and 204), suchthat the corresponding subgrating pitch is 3*GPGP.

As shown in FIG. 2, linear layout shapes are initially placed in acentered manner on the subgrating of the subgrating region in which thelinear layout shape is placed. Also, it should be appreciated from theexample of FIG. 2 that layout shapes of uniform width placed inaccordance with the same subgrating can have a common run length. Also,layout shapes that are placed on the same virtual line of the GPG inadjacent subgrating regions may, if necessary, be extended through theinterface between the adjacent subgrating regions so as to combine andform single contiguous layout shape that spans the interface between theadjacent subgrating regions. For example, FIG. 2 shows layout shapes250A and 250B extending through the interface between adjacentsubgrating regions 222 and 224 so as to form a single layout shape 250.

It should be understood that a subgrating region is defined as acontiguous area within a layout of a portion of a given chip level inwhich layout shapes are aligned to a common subgrating. It should alsobe understood that a subgrating region can be defined to have anarbitrary shape. However, in one embodiment, an effort is made to definesubgrating regions such that a minimal number of boundary segments areused to define a periphery of each subgrating region. Also, in oneembodiment, when possible, layout shapes having related functions aregrouped together within a subgrating region so as to maximize subgratingregion area and minimize the number of boundary segments betweenadjacent subgrating regions. Moreover, it is likely that connectionpoints utilizing the same subgrating will have related or identicalfunctions. Also, in one embodiment, fill shapes neighboring a givensubgrating region are placed in accordance with the given subgratingregion so as to further maximize the area of the given subgratingregion.

When layout shapes are placed according to a subgrating, a situation mayarise in which the subgrating pitch and the layout shape width result ina side-to-side spacing between adjacently placed layout shapes that istoo large to ensure proper manufacturability of the layout shapes. FIG.3A shows an example in which a subgrating pitch (SGP) results in a ratioof side-to-side spacing (S1) to layout shape width (W) that is too largeto maintain sufficient shape density for proper manufacturing.

FIG. 3B shows a modification of the layout of FIG. 3A in which asubresolution shape 301 is used to mitigate the unacceptably large ratio(S1/W), in accordance with one embodiment of the present invention. Thesubresolution shape 301 is defined to have a width (SRW) that is smallenough to ensure that subresolution shape 301 will not be manufactured.Also, the subresolution shape 301 is placed such that a side-to-sidespacing (S2) with its neighboring layout shapes is optimized formanufacturability of the neighboring layout shapes. Also, in someembodiments, because the width (SRW) of the subresolution shape 301primarily governs whether or not the subresolution shape 301 willactually resolve, i.e., be manufactured, a length (SL) of thesubresolution shape 301 can be made as large as necessary withoutincreasing a likelihood that the subresolution shape 301 isinadvertently manufactured. The presence of the subresolution shape 301will serve to enhance manufacturability of its neighboring layout shapesduring a lithographic manufacturing process. It should be understood,however, that subresolution shapes are not intended to be manufacturedand should not be placed or sized to cause their manufacture. Moreover,the likelihood of subresolution shape being manufactured can bedependent upon a layout shape density in its surrounding neighborhood.Therefore, the placement and sizing of a given subresolution shapeshould consider the layout shape density around the given subresolutionshape.

In one embodiment, a subresolution shape can be placed within asubgrating region without regard to the corresponding subgrating for thepurpose of enhancing manufacturability of layout shapes within thesubgrating region. In another embodiment, a subresolution shape can beplaced within a subgrating region in accordance with the correspondingsubgrating for the purpose of enhancing manufacturability of layoutshapes within the subgrating region.

FIG. 4 shows an example layout in which a GPG is used to place layoutshapes for gate electrode wires (“gates” hereafter), interconnect wires,diffusion contacts, and gate contacts, in accordance with one embodimentof the present invention. The GPG is defined by virtual lines 401-406evenly spaced at GPG pitch (GPGP). Gate wires 410 are placed accordingto a subgrating SG-A within the gate chip level that includes everyother even numbered virtual line of the GPG (GPG virtual lines 402, 404,406), such that the corresponding subgrating pitch is 2*GPGP.Interconnect wires 420 are also placed according to the subgrating SG-Awithin a given interconnect chip level that includes every other evennumbered virtual line of the GPG (GPG virtual lines 402, 404, 406).Interconnect wires 430 are placed according to a subgrating SG-B withinthe given interconnect chip level that includes every other odd numberedvirtual line of the GPG (GPG virtual lines 401, 403, 405), such that thecorresponding subgrating pitch is 2*GPGP. Diffusion contacts 440, i.e.,source/drain contacts, are also placed according to the subgrating SG-Bwithin the diffusion contact chip level that includes every other oddnumbered virtual line of the GPG (GPG virtual lines 401, 403, 405). Gatecontacts 450 are placed according to the subgrating SG-A within the gatecontact chip level that includes every other even numbered virtual lineof the GPG (GPG virtual lines 402, 404, 406).

In one embodiment, layout shapes and subgratings within a portion of agiven chip level are defined to enable use of substantially uniformlayout shapes widths, substantially uniform layout shape side-to-sidespacings, and substantially uniform layout shape end-to-end spacings.For example, the embodiment of FIG. 4 shows use of a substantiallyuniform interconnect wire layout shape width (M1W) within theillustrated portion of the interconnect chip level. Also, FIG. 4 showsuse of a substantially uniform interconnect layout shape side-to-sidespacing (M1S) within the illustrated portion of the interconnect chiplevel. Also, FIG. 4 shows use of a substantially uniform interconnectlayout shape end-to-end spacing (M1LES) within the illustrated portionof the interconnect chip level.

Additionally, FIG. 4 shows use of a substantially uniform gate wirelayout shape width (GW) within the illustrated portion of the gate chiplevel. Also, FIG. 4 shows use of a substantially uniform gate layoutshape side-to-side spacing (GS) within the illustrated portion of thegate chip level. Also, FIG. 4 shows use of a substantially uniform gatelayout shape end-to-end spacing (GLES) within the illustrated portion ofthe gate chip level. In various embodiments, extension of a layout shapesize through stretching of one or more of the layout shape's edges canbe used to achieve the substantially constant layout shape widths,side-to-side spacings, and end-to-end spacings. Moreover, althoughmanufacturing benefits (such as in lithography processes) may beachieved by using substantially constant layout shape widths,side-to-side spacings, and end-to-end spacings, it should be understoodthat use of GPGs, subgratings, and subgrating regions does not requireuse of substantially constant layout shape widths, side-to-sidespacings, and end-to-end spacings.

FIG. 5 shows an extension of the exemplary layout of FIG. 4 in which anumber of subgrating regions are defined in various chip levels, inaccordance with one embodiment of the present invention. A diffusionlevel of the exemplary layout includes diffusion regions 502 and 504. Agate level of the exemplary layout includes the gate wire layout shapes410. A single subgrating region 507 is defined for the gate level, withthe subgrating SG-A allocated thereto. Three subgrating regions 501,503, 505 are defined for each of the diffusion contact level, gatecontact level, and interconnect level with the subgratings SG-B, SG-A,SG-B allocated thereto, respectively. Therefore, each of the chip levelsof the exemplary layout of FIG. 5 is partitioned into a number ofsubgrating regions, wherein each of these subgrating regions is definedas a contiguous area within the layout.

FIG. 5 also illustrates how layout shapes of related function can beplaced together within a common subgrating region. For example,diffusion contacts 440 and their associated interconnect wires 430 areplaced together in each of subgrating regions 501 and 505 in accordancewith subgrating SG-B. Also, gate contacts 450 and their associatedinterconnect wires 420 are placed together in subgrating region 503 inaccordance with subgrating SG-A. The gate wires 410 are placed insubgrating region 507 in accordance with subgrating SG-A. Based on theexample of FIG. 5, it should be appreciated that allocation of aproperly defined subgrating to a given subgrating region provides forplacement of layout shapes having a common run length within the givensubgrating region.

A layout shape in one subgrating region of a given chip level canconnect with another layout shape in an adjacent subgrating region ofthe given level when the two layout shapes are placed along the samevirtual line of the GPG, thereby forming a larger shape that traversesacross the interface between the adjacent subgrating regions. This isillustrated above with regard to layout shapes 250A and 250B of FIG. 2combining to form layout shape 250. Therefore, a layout shape can bedefined to cross from one subgrating region to an adjacent subgratingregion in a given level when the different subgratings in the adjacentsubgrating regions align to a common GPG virtual line.

The techniques described herein may be generalized to enable patternregularity for any number of chip levels that are partitioned intosubgrating regions. FIG. 6 shows an example layout that illustratessubgrating use among different vertically stacked chip levels, inaccordance with one embodiment of the present invention. As shown inFIG. 6, a metal-3 subgrating region 620 includes vias 630 that connectto metal-2 wires 631 centered on horizontal GPG virtual line 650. Thevias 630 and metal-3 wires 632 that overlap them are centered on oddnumbered vertical GPG virtual lines 611, 613, 615, respectively, andhave a horizontal pitch M3P2 that is twice the vertical GPG pitch GPG2.In another metal-3 subgrating region 621, vias 633 that connect tometal-2 wires 634 are centered on horizontal GPG virtual line 651, andthe metal-3 wires 635 that overlap them are centered on even numberedvertical GPG virtual lines 610, 612, 614, respectively, and have ahorizontal pitch M3P1 that is twice the vertical GPG pitch GPG2.

FIG. 7 shows an example layout in which a multi-level orthogonallyrouted connection is used to connect wires in a same chip level thatcannot have a common run length, in accordance with one embodiment ofthe present invention. Parallel metal-1 layout shapes 702, 701, 700 arecentered on adjacent GPG virtual lines 740, 741, 742, respectively, andhave insufficient clearance to run side-by-side, i.e., to have a commonrun length. Therefore, the metal-1 layout shapes 700, 701, 702 cannottraverse the boundary between the adjacent subgrating regions 760 and761, and therefore cannot make a physical connection to each otherwithin their chip level.

One solution is to use multiple chip levels with orthogonal routingdirections to make the required connections. For example, as shown inFIG. 7, a diffusion shape 704 is connected to gate wire 720 byconnecting through each of diffusion contact 710, metal-1 wire 701, via730, metal-2 wire 740, via 750, metal-3 wire 770, via 751, metal-2 wire741, via 731, metal-1 wire 702, and contact 711. This multiple chiplevel orthogonal routing connection solution can be generalized to formconnections when layout shapes on a given level cannot traverse asubgrating region boundary that crosses their routing direction, i.e.,when layout shapes on a given level cannot have a common run length.

FIG. 8 shows another example layout in which a multi-level orthogonallyrouted connection is used to connect wires in a same chip level thatcannot have a common run length, in accordance with one embodiment ofthe present invention. Parallel metal-3 wires 800-803 centered onadjacent GPG lines 870-873 cannot traverse the boundary 880 betweenmetal-3 subgrating regions 820 and 821. Therefore, due to the boundary880, a direct connection cannot be made between metal-3 wires 801 and802. However, a connection can be made between metal-3 wires 801 and 802by connecting through each of the following elements: via 830, metal-2wire 840, via 850, metal-1 wire 860, via 851, metal-2 wire 841, and via831. FIG. 8 also shows that wires on different levels with identicalrouting directions such as metal-1 wires 860-862 and metal-3 wires800-803 may be centered on different GPGs such as the GPG with pitchGRM3 for metal-3 and the GPG with pitch GRM1 for metal-1.

In one embodiment, the GPG and subgrating region techniques describedabove can be used to enforce the following layout shape patternregularity conventions that are beneficial to manufacturing: 1) layoutshapes are rectangular, i.e., linear-shaped, 2) wire layout shape pitchis substantially constant in the direction orthogonal to routing, 3)contact layout shape pitch is substantially constant in the directionorthogonal to routing, 4) wire layout shape width is substantiallyconstant, 5) wire layout shape side-to-side spacing is substantiallyconstant, 6) wire layout shape end-to-end spacing is substantiallyconstant, and 7) overall layout shape density is as uniform as possible.

FIG. 9A shows an example layout that illustrates the occurrence of anon-standard spacing at an interface between adjacent subgratingregions, in accordance with one embodiment of the present invention. Inthe example of FIG. 9A, a metal-1 subgrating region 900 that includesgate contacts 940 centered on even numbered GPG lines 924, 926, and ametal-1 subgrating region 901 that includes diffusion contacts 950centered on odd GPG lines 921, 923. The metal-1 subgrating region 901borders the metal-1 subgrating region 900 both vertically andhorizontally. This introduces a non-standard spacing, M1S2, straddlingthe horizontal subgrating regional border located between the metal-1wires 910 and 912.

FIG. 9B shows a layout shape stretching technique for mitigating anon-standard spacing introduced at subgrating region borders that lieparallel to the routing direction, in accordance with one embodiment ofthe present invention. The layout of FIG. 9B is a modified version ofthe metal-1 layout of FIG. 9A. In FIG. 9B, the edge of metal-1 wire 910that faces the large gap is stretched until it is co-linear with theedge of a metal-1 wire 911, which faces the same gap but is centered onan alternate grating line 923. By stretching the metal-1 wire 910, wirespaces M1S are made constant, but the metal-1 wire 910 has non-standardwidth and is no longer centered on a GPG line. However, the stretchingof the metal-1 wire 910 in favor of constant spacing provides an overallimprovement in manufacturability.

FIG. 10A shows an example layout that illustrates the occurrence of anon-standard spacing at an interface between adjacent subgratingregions, when the layout shape stretching technique of FIG. 9B isblocked, in accordance with one embodiment of the present invention. InFIG. 10A, layout shape 1010 in subgrating region 1000 runs parallel to alayout shape 1012 in subgrating region 1001, wherein layout shapes 1010and 1012 are aligned to different subgratings. The non-standard gap M1S2extends along the common run length CRL of layout shapes 1010 and 1012.The layout shape 1010 cannot be stretched toward the layout shape 1012to reduce M1S2 because it is blocked by another layout shape 1013 in thesame subgrating region 1000.

Due to the application of a GPG and fixed layout shape widths, M1S2 ismost likely limited to a fixed value. In the example of FIG. 10A,M1S2=3*GPGP-M1W. More specifically, the fixed value for M1S2 applies toregions of the chip that share the same GPGP and M1W values. Thus, itshould be appreciated that even when non-standard gaps, e.g., M1S2,cannot be mitigated through layout shape modification (such as layoutshape stretching), specification of a constant GPGP value and of alimited number of layout shape widths, e.g., M1W, will serve to limitthe corresponding number of non-standard gap values that may occur inthe layout. For instance, in the example of FIG. 10A, use of theconstant GPGP value and the single layout shape width M1W serves tolimit the number of non-standard gap values to one, i.e., to the M1S2value. Therefore, through specification of a constant GPGP value and ofa limited number of layout shape widths it is possible to optimizemanufacturing processes to account for a controlled number ofnon-standard spacings that may occur in the layout. In contrast, itshould be appreciated that such manufacturing process optimization isnot feasible when an uncontrolled number of non-standard layout shapespacings may occur in a given layout.

FIG. 10B illustrates use of a subresolution shape to mitigate anon-standard spacing at an interface between adjacent subgratingregions, as an alternative to the layout shape stretching technique ofFIG. 9B is blocked, in accordance with one embodiment of the presentinvention. The layout of FIG. 10B is a modified version of the layout ofFIG. 10A. In FIG. 10B, a sub-resolution layout shape 1014 is placedwithin the area corresponding to the non-standard spacing. As with theprevious subresolution layout shape description of FIG. 3B, a width(SRW) of the subresolution layout shape 1014 should be small enough toensure that the subresolution layout shape 1014 is not manufactured. Itshould be appreciated that overall layout shape density and layout shapeside-to-side spacing M1S can be made substantially uniform through useof this subresolution layout shape insertion technique. It should beunderstood, however, that in some embodiments the presence of anon-standard spacing at subgrating region boundaries is acceptable anddoes not require mitigation.

FIG. 11 shows an exemplary layout in which a layout shape is stretchedto overlap multiple contacts and/or vias, in accordance with oneembodiment of the present invention. In one embodiment, a linear layoutshape of a wire can be stretched orthogonally to its preferred routingdirection so that it overlaps multiple contacts and/or vias. Forexample, FIG. 11 shows a metal-1 wire 1110 having a preferred horizontalrouting direction, i.e., preferred x-direction of routing. The metal-1wire 1110 is placed in a subgrating region 1100 that is defined adjacentto a subgrating region 1103. The metal-1 wire 1110 needs to connect toeach of contacts 1120 and 1121. While the metal-1 wire 1110 may havebeen initially placed in a centered manner on a GPG virtual line, themetal-1 wire 1110 is stretched orthogonal to its preferred routingdirection, i.e., is stretched in the y-direction, so as to cover both ofcontacts 1120 and 1121. It should be understood that the linear layoutshape stretching technique, exemplified by the metal-1 wire 1110 of FIG.11, can be generalized to facilitate connection of layout shapes withindifferent chip levels, within different subgrating regions of a givenchip level, or within a same subgrating region of a given chip level.

FIG. 12 shows another example in which layout shapes are stretched tooverlap multiple contacts and/or vias, in accordance with one embodimentof the present invention. In FIG. 12, a metal-2 wire layout shape 1231is stretched in the x-direction, i.e., widened, such that both of itsedges maintain a standard spacing M2S to adjacent wire layout shapes1232 and 1233, and such that it overlaps and connects with a via 1240and a via 1241. In this manner, the metal-2 wire 1231 serves to connecta metal-3 wire 1261 in a metal-3 subgrating region 1270 to a metal-3wire 1262 in a metal-3 subgrating region 1271. Also, a metal-2 wirelayout shape 1230 is similarly widened to overlap and connect with a via1250 and a via 1242, which are respectively connected to a metal-1 wire1220 and a metal-3 wire 1260.

FIG. 13 shows an example in which layout shapes are extended relative toa contact and/or via so as to accommodate design requirements, inaccordance with one embodiment of the present invention. Two adjacentsubgrating regions 1300 and 1301 are defined for a metal-1 chip level. Adiffusion contact 1311 is defined to connect a diffusion region 1323 toa metal-1 wire 1321. The diffusion contact 1311 is covered by themetal-1 wire 1321 layout shape. Given a lack of metal-1 wire 1321overlap of the contact 1311 in the y-direction, a horizontal extensionM1OL of the metal-1 wire 1321 layout shape in the x-direction isprovided to enable compliance with design rules. Also, a gate contact1310 is defined to connect a gate wire 1322 to a metal-1 wire 1320. Themetal-1 wire 1320 layout shape can be defined to minimally overlap thegate contact 1310 in the x-direction due to the significant overlap ofthe gate contact 1310 by the metal-1 wire 1320 layout shape in they-direction.

It should be understood that the manufacturability benefits of layouttechniques described herein are preserved if dimensions referred to assubstantially constant are allowed to vary slightly, so long as generallayout pattern regularity is preserved. In one embodiment, the followinglayout method can be used for chip levels that are to be routedaccording to a GPG that is defined by a pitch too small to allow forcommon run lengths of shapes placed on adjacent GPG virtual lines.First, subgratings are defined. In one embodiment, alternate GPG linesare used for alternate functions when defining the subgratings. Then,layout shapes are organized according to subgrating regions. In oneembodiment, layout shapes that use the same set of GPG virtual lines aregrouped together in subgrating regions. Multiple chip levels can beutilized to make connections between layout shapes of a given chip levelwhen required due to fragmentation of those layout shapes at subgratingregion boundaries within the given chip level.

Additionally, after initial layout shape placement, layout shapes can bestretched, i.e., widened, so as to maintain substantially constantside-to-side spacing where necessary, such as at subgrating regionboundaries that run parallel to the preferred routing direction. In someinstances, non-standard spaces between layout shapes at subgratingregion boundaries can be accepted when those non-standard spaces arepredictable and fixed. Also, in some instances, non-standard spacesbetween layout shapes at subgrating region boundaries can be partiallyfilled using subresolution layout shapes. Moreover, in some instances,layout shapes neighboring non-standard spaces at subgrating regionboundaries can be stretched so as to mitigate the non-standard spaces.Furthermore, a layout shape can be stretched, i.e., widened, in thedirection orthogonal to its preferred routing direction so as to allowfor connection of multiple overlapping contacts and/or vias to thelayout shape. Also, a layout shape can be stretched, i.e., widened, inthe direction orthogonal to its preferred routing direction so as toallow for reduction of contact and/or via overlap/extension by thelayout shape in the direction parallel to its preferred routingdirection.

FIG. 14 shows a flowchart of a method for defining a layout for aportion of a given semiconductor chip level, in accordance with oneembodiment of the present invention. The method includes an operation1401 for defining a preferred routing direction for a given chip level.The method also includes an operation 1403 for identifying each contactlevel related to the given chip level, wherein such a related contactlevel includes at least one interfacing contact defined to physicallyconnect with a structure corresponding to a layout shape to be placed inthe given chip level. In various embodiments, contact levels related tothe given chip level can include a gate contact level, a diffusioncontact level, a via level, or a combination thereof.

The method further includes an operation 1405 for defining a globalplacement grating (GPG) for the given chip level to include a set ofparallel and evenly spaced virtual lines. The GPG is defined such thatat least one virtual line of the GPG is positioned to intersect eachinterfacing contact within each contact level that is related to thegiven chip level, as identified in operation 1403. An operation 1407 isthen performed to determine whether a perpendicular spacing betweenadjacent virtual lines of the GPG, i.e., GPG pitch, provides forenforcement of layout shape pattern regularity within the given chiplevel as necessary to ensure manufacturability of layout shapes withinthe given chip level.

It should be understood that what constitutes sufficient layout shapepattern regularity can be dependent upon many factors, such as acritical dimension of structures to be defined in the chip, a spacingbetween structures to be defined in the chip, and/or a function ofstructures to be defined in the chip, among others. Thus, it should beunderstood that what constitutes sufficient layout shape patternregularity can vary from one design to another. In one particularembodiment, enforcement of layout shape pattern regularity within agiven chip level includes one or more of 1) a substantially constantlayout shape width as measured perpendicular to the preferred routingdirection, 2) a substantially constant spacing between adjacently placedlayout shapes as measured perpendicular to the preferred routingdirection, and 3) a substantially constant spacing between ends ofadjacently placed layout shapes as measured parallel to the preferredrouting direction. An example of this embodiment is illustrated in FIG.4, as previously described.

If operation 1407 determines that the perpendicular spacing betweenadjacent virtual lines of the global placement grating is notacceptable, the method proceeds with an operation 1411 for adjustment ofthe placement(s) of one or more contacts that interface with the givenchip level. Then, the method reverts back to operation 1405 and proceedsas described above.

If operation 1407 determines that the perpendicular spacing betweenadjacent virtual lines of the global placement grating is acceptable,the method proceeds with an operation 1409 in which layout shapes areplaced in alignment with the GPG for the given chip level. In oneembodiment, the layout shapes placed in alignment with the GPG aredefined as linear layout shapes having a substantially rectangularcross-section when viewed in an as-drawn state. Also, in one embodiment,each linear layout shape is placed such that a length of itssubstantially rectangular cross-section is parallel with the preferredrouting direction. Additionally, in one embodiment, each linear layoutshape is initially placed such that its centerline extending in thepreferred routing direction is substantially centered upon a virtualline of the GPG. It stood be understood, however, that after initialplacement, some of the linear layout shapes may be stretched orotherwise modified to mitigate non-standard spacings within the layoutso as to provide for sufficient layout shape pattern regularity asnecessary to ensure manufacturability of layout shapes within the givenchip level.

FIG. 15A shows a flowchart of a method for defining a layout for aportion of a given semiconductor chip level, in accordance with oneembodiment of the present invention. The method includes an operation1501 for defining a global placement grating (GPG) for a given chiplevel. The GPG is defined by a set of parallel and evenly spaced virtuallines. The method also includes an operation 1503 for identifying allconnection lines within the GPG. A connection line is a virtual line ofthe GPG that is spatially coincident with a virtual line of a relatedcontact level. A related contact level includes at least one contactthat is defined to physically connect with a structure corresponding toa layout shape placed within the given chip level. The virtual lines ofany given related contact level are defined as a set of parallel andequally spaced virtual lines to which contact layout shapes are aligned.

The method further includes an operation 1505 for defining a subgratingfor the given chip level. A subgrating is defined as a set of evenlyspaced connection lines, such that a spacing between adjacent connectionlines in the subgrating is at least as large as a minimum spacingrequired to support a common run length of layout shapes on the adjacentconnection lines in the subgrating. A common run length of two layoutshapes occurs where the two layout shapes are placed in a side-by-sidemanner on adjacent connection lines in the subgrating. In oneembodiment, defining a subgrating for a chip level includes associatingthe subgrating with a particular function to be performed by structurescorresponding to layout shapes to be placed in accordance with the givensubgrating. Also, in this embodiment, a perpendicular spacing betweenadjacent lines of the given subgrating is defined to accommodateplacement of the layout shapes corresponding to the particular function.

Following operation 1505, the method proceeds with a decision operation1507 for determining whether each connection line within the globalplacement grating is associated with at least one subgrating. If eachconnection line is not associated with at least one subgrating themethod reverts back to proceed again with operation 1505. However, ifeach connection line is associated with at least one subgrating, themethod proceeds with operation 1509 for placing layout shapes inalignment with the defined subgratings, such that each layout shape isassociated with any one subgrating.

In one embodiment, each layout shape of the given chip level is placedin alignment with at least one subgrating for the given chip level andis defined as a linear layout shape having a substantially rectangularcross-section when viewed in an as-drawn state. Each linear layout shapeis placed such that its lengthwise centerline extends parallel to thevirtual lines of the GPG. Also, each linear layout shape is initiallyplaced such that its lengthwise centerline is substantially centeredupon a line of its subgrating.

FIG. 15B shows an expanded view of operation 1509, in accordance withone embodiment of the present invention. In an operation 1511, thelayout for the given chip level is partitioned into a number ofsubgrating regions. Each subgrating region is defined as a contiguousarea within the layout for the given chip level. An operation 1513 isperformed to allocate subgratings to the number of subgrating regions,such that only one subgrating is allocated to any one subgrating region.It should be understood, however, that different subgrating regions canhave different subgratings respectively allocated thereto. In oneembodiment, each of the number of subgrating regions within the givenchip level is defined such that a layout area of each subgrating regionis made as large as possible while accommodating layout arearequirements of every other subgrating region within the given chiplevel. Also in this embodiment, the subgrating regions within the givenchip level are defined such that a minimal number of boundary segmentsare used to define a periphery of each subgrating region.

Once the subgrating regions are defined and have subgratings allocatedthereto, the method proceeds with an operation 1515 for placing a firstset of layout shapes for the given chip level. Each layout shape of thefirst set is aligned to the subgrating for the subgrating region inwhich the layout shape is placed. In one embodiment, each layout shapeof the given chip level is placed according to the followingspecifications: 1) the layout shape is placed in alignment with at leastone subgrating for the given chip level and is defined as a linearlayout shape having a substantially rectangular cross-section whenviewed in an as-drawn state, 2) the layout shape is placed such that itslengthwise centerline extends parallel to the virtual lines of the GPG,3) the layout shape is initially placed such that its lengthwisecenterline is substantially centered upon a line of its subgrating.

In one augmentation of the above-described embodiment, a particularlinear layout shape of the given chip level is stretched in itswidthwise direction extending perpendicular to the virtual lines of theGPG, after the initial placement of the particular linear layout shape,such that a structure corresponding to the particular linear layoutshape will physically connect with multiple contacts (i.e., contactsand/or vias) within one or more related contact levels. An example ofthis is illustrated in FIG. 11 by the stretching of layout shape 1110 tocover and physically connect with contacts 1120 and 1121. In anotheraugmentation of the above-described embodiment, a particular linearlayout shape of the given chip level is stretched in its widthwisedirection extending perpendicular to the virtual lines of the GPG, afterthe initial placement of the particular linear layout shape, such that astructure corresponding to the particular linear layout shape willsufficiently overlap one or more contacts (i.e., contacts and/or vias)within one or more related contact levels. An example of this isillustrated in FIG. 13 by the stretching of layout shape 1320 tosufficiently overlap contact 1310.

Additionally, in one embodiment, some layout shapes in adjacentsubgrating regions that are placed on a common virtual line of the GPGare extended through a boundary between the adjacent subgrating regionsso as to form a single contiguous layout shape. In yet anotherembodiment, two or more layout shapes respectively placed in adjacentsubgrating regions of the given chip level and on different virtuallines of the GPG are electrically connected together by orthogonallyrouted structures that extend through multiple chip levels. In thisembodiment, the subgratings of the adjacent subgrating regions may notaccommodate a common run length of the two or more layout shapes.

FIG. 15C shows an extension of the method of FIGS. 15A-15B, inaccordance with various embodiments of the present invention. In oneembodiment, the method proceeds from operation 1515 with an operation1517 for identifying a blank space within the layout of the given chiplevel. The blank space in this embodiment is identified as a spatialarea within the layout of the given chip level at which a non-standardspacing exists between layout shapes of the first set as placed inoperation 1515. The method then proceeds with an operation 1519 foridentifying a subgrating associated with a neighboring layout shape ofthe first set relative to the blank space and proximate to the blankspace. An operation 1521 is then performed to define a second set oflayout shapes for the given chip level within the blank space. Thesecond set of layout shapes are placed in alignment with the subgratingidentified in operation 1519. The second set of layout shapes aredefined within the blank space so as to optimize manufacturability ofthe first set of layout shapes. In one embodiment, operations 1517through 1521 are repeated until each blank space within the given chiplevel has been considered for placement of one or more layout shapes ofthe second set therein.

In another embodiment, the method proceeds from operation 1515 with anoperation 1525 for identifying a non-standard spacing within the layoutof the given chip level at an interface between adjacent subgratingregions. The method then proceeds with an operation 1527 for identifyinga layout shape adjacent to the non-standard spacing that can bestretched toward the interface between the adjacent subgrating regions.An operation 1529 is then performed to stretch the layout shapeidentified in operation 1527 toward the interface between the adjacentsubgrating regions so as to mitigate the non-standard spacing. In oneembodiment, the layout shape identified in operation 1527 is stretchedwithin its subgrating region so as to align with another layout shapepresent in the adjacent subgrating region. In one embodiment the layoutshape identified in operation 1527 is a linear layout shape and isstretched in its widthwise direction that extends perpendicular to thevirtual lines of the GPG.

In yet another embodiment, the method proceeds from operation 1515 withan operation 1531 for identifying a non-standard spacing within thelayout of the given chip level at an interface between adjacentsubgrating regions. The method then proceeds with an operation 1533 foridentifying an inability to stretch a layout shape adjacent to thenon-standard spacing toward the interface between the adjacentsubgrating regions. An operation 1535 is then performed to define asubresolution layout shape within a layout area of the given chip levelcorresponding to the non-standard spacing. The subresolution shape isdefined to reinforce manufacturability of the first set of layout shapesnear the non-standard spacing, and so as to ensure that thesubresolution layout shape is not manufactured.

In yet another embodiment, following operation 1515, one or morenon-standard spacings are identified within the layout of the given chiplevel. In this embodiment, a decision is made to not mitigate theidentified non-standard spacings. For example, the identifiednon-standard spacings may be dealt with through optimization of one ormore manufacturing processes without requiring modification of thelayout of the given chip level.

FIG. 16 shows a flowchart of a method for defining a layout for aportion of a given semiconductor chip level, in accordance with oneembodiment of the present invention. The method includes an operation1601 for defining a global placement grating (GPG) for a given chiplevel, wherein the global placement grating is defined by a set ofparallel and evenly spaced virtual lines. The method also includes anoperation 1603 for identifying all connection lines within the GPG. Aconnection line is a virtual line of the GPG that is spatiallycoincident with a virtual line of a related contact level. The methodfurther includes an operation 1605 for defining a subgrating for thegiven chip level as a set of evenly spaced connection lines, such that aspacing between adjacent connection lines in the subgrating is at leastas large as a minimum spacing required to support a common run length oflayout shapes on the adjacent connection lines in the subgrating.

A decision operation 1607 is provided to determine whether or not eachconnection line within the GPG is associated with at least onesubgrating. If each connection line within the GPG is not associatedwith at least one subgrating, the method reverts back to operation 1605.If each connection line within the GPG is associated with at least onesubgrating, the method continues with an operation 1609 for partitioningthe layout for the given chip level into a number of subgrating regions.Each subgrating region is defined as a contiguous area within the layoutfor the given chip level. An operation 1611 is then performed toallocate subgratings to the number of subgrating regions such that onlyone subgrating is allocated to any one subgrating region. It should beunderstood that different subgratings can be allocated to differentsubgrating regions, so long as no more than one subgrating is allocatedto a given subgrating region in a given chip level.

The method continues with an operation 1613 for placing functionallayout shapes for the given chip level in alignment to the subgratingsallocated to the subgrating regions. Following placement of thefunctional layout shapes in operation 1613, the method proceeds with anoperation 1615 for identifying a non-standard spacing within the layoutof the given chip level. In one embodiment, identifying the non-standardspacing in operation 1615 includes comparing a side-to-side spacing offunctional layout shapes located adjacent to each subgrating regioninterface extending parallel to the virtual lines of the GPG with astandard side-to-side spacing between (or specified for) adjacentfunctional layout shapes within the given chip level.

In one embodiment, an operation 1617 is then performed to resolve thenon-standard spacing so as to optimize manufacturability of structurescorresponding to the functional layout shapes. In various embodiments,resolving the non-standard spacing in operation 1617 can include eitherstretching a functional layout shape to reduce the non-standard spacing,or inserting a non-functional layout shape within the non-standardspacing, or inserting a subresolution shape within the non-standardspacing, or a combination thereof.

In an alternative embodiment, operation 1617 includes making a decisionto not mitigate the identified non-standard spacing. For example, theidentified non-standard spacing may be dealt with through adjustment ofone or more manufacturing processes without requiring modification ofthe layout of the given chip level.

In one embodiment, each functional layout shape of the given chip levelis placed in alignment with at least one subgrating for the given chiplevel and is defined as a linear layout shape having a substantiallyrectangular cross-section when viewed in an as-drawn state. Also in thisembodiment, each functional layout shape is placed such that itslengthwise centerline extends parallel to the virtual lines of the GPG.Also in this embodiment, each functional layout shape is initiallyplaced (prior to operation 1617) such that its lengthwise centerline issubstantially centered upon a line of its subgrating.

It should be understood that the chip layouts generated by the methodsdisclosed herein can be stored in a tangible form, such as in a digitalformat on a computer readable medium. Also, the invention describedherein can be embodied as computer readable code on a computer readablemedium. The computer readable medium is any data storage device that canstore data which can thereafter be read by a computer system. Examplesof the computer readable medium include hard drives, network attachedstorage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs,CD-RWs, magnetic tapes, and other optical and non-optical data storagedevices. The computer readable medium can also be distributed over anetwork of coupled computer systems so that the computer readable codeis stored and executed in a distributed fashion.

Any of the operations described herein that form part of the inventionare useful machine operations. The invention also relates to a device oran apparatus for performing these operations. The apparatus may bespecially constructed for the required purpose, such as a specialpurpose computer. When defined as a special purpose computer, thecomputer can also perform other processing, program execution orroutines that are not part of the special purpose, while still beingcapable of operating for the special purpose. Alternatively, theoperations may be processed by a general purpose computer selectivelyactivated or configured by one or more computer programs stored in thecomputer memory, cache, or obtained over a network. When data isobtained over a network the data maybe processed by other computers onthe network, e.g., a cloud of computing resources.

The embodiments of the present invention can also be defined as amachine that transforms data from one state to another state. The datamay represent an article, that can be represented as an electronicsignal and electronically manipulate data. The transformed data can, insome cases, be visually depicted on a display, representing the physicalobject that results from the transformation of data. The transformeddata can be saved to storage generally, or in particular formats thatenable the construction or depiction of a physical and tangible object.In some embodiments, the manipulation can be performed by a processor.In such an example, the processor thus transforms the data from onething to another. Still further, the methods can be processed by one ormore machines or processors that can be connected over a network. Eachmachine can transform data from one state or thing to another, and canalso process data, save data to storage, transmit data over a network,display the result, or communicate the result to another machine.

While this invention has been described in terms of several embodiments,it will be appreciated that those skilled in the art upon reading thepreceding specifications and studying the drawings will realize variousalterations, additions, permutations and equivalents thereof. Therefore,it is intended that the present invention includes all such alterations,additions, permutations, and equivalents as fall within the true spiritand scope of the invention.

What is claimed is:
 1. A semiconductor device, comprising: a first gateconductive structure defined in a gate level of the semiconductordevice, the first gate conductive structure having a linear-shape and alengthwise centerline oriented in a first direction parallel to asubstrate of the semiconductor device; a second gate conductivestructure defined in the gate level of the semiconductor device, thesecond gate conductive structure having a linear-shape and a lengthwisecenterline oriented in the first direction, the lengthwise centerline ofthe second gate conductive structure separated from the lengthwisecenterline of the first gate conductive structure by a first distance asmeasured in a second direction, the second direction orientedperpendicular to the first direction and parallel to the substrate ofthe semiconductor device; a first diffusion region positioned along aportion of a first side of the first gate conductive structure; a seconddiffusion region positioned along a portion of a second side of thefirst gate conductive structure, the second diffusion region alsopositioned along a portion of a first side of the second gate conductivestructure, wherein the first gate conductive structure and the firstdiffusion region and the second diffusion region together form a firsttransistor; a third diffusion region positioned along a portion of asecond side of the third gate conductive structure, wherein the secondgate conductive structure and the second diffusion region and the thirddiffusion region together form a second transistor; a first interconnectconductive structure defined in an interconnect level of thesemiconductor device, the interconnect level of the semiconductor devicepositioned above the gate level of the semiconductor device, the firstinterconnect conductive structure having a linear-shape and a lengthwisecenterline oriented in the first direction, the lengthwise centerline ofthe first interconnect conductive structure separated from thelengthwise centerline of the first gate conductive structure by one-halfof the first distance as measured in the second direction, the firstinterconnect conductive structure having a width measured in the seconddirection that is at least twice a width of the first gate conductivestructure as measured in the second direction; a second interconnectconductive structure defined in the interconnect level of thesemiconductor device, the second interconnect conductive structurehaving a linear-shape and a lengthwise centerline oriented in the firstdirection, the lengthwise centerline of the second interconnectconductive structure separated from the lengthwise centerline of thefirst gate conductive structure by one-half of the first distance asmeasured in the second direction, the lengthwise centerline of thesecond interconnect conductive structure separated from the lengthwisecenterline of the third gate conductive structure by one-half of thefirst distance as measured in the second direction, the secondinterconnect conductive structure having a width measured in the seconddirection that is at least twice the width of the first gate conductivestructure as measured in the second direction; and a third interconnectconductive structure defined in the interconnect level of thesemiconductor device, the third interconnect conductive structure havinga linear-shape and a lengthwise centerline oriented in the firstdirection, the lengthwise centerline of the third interconnectconductive structure separated from the lengthwise centerline of thesecond gate conductive structure by one-half of the first distance asmeasured in the second direction, the third interconnect conductivestructure having a width measured in the second direction that is atleast twice the width of the first gate conductive structure as measuredin the second direction.
 2. The semiconductor device as recited in claim1, wherein each of the first diffusion region, and the second diffusionregion, and the third diffusion region has a substantially equal size asmeasured in the first direction.
 3. The semiconductor device as recitedin claim 1, further comprising: a first diffusion contact extendingbetween the first diffusion region and the first interconnect conductivestructure; a second diffusion contact extending between the seconddiffusion region and the second interconnect conductive structure; and athird diffusion contact extending between the third diffusion region andthe third interconnect conductive structure.
 4. The semiconductor deviceas recited in claim 3, wherein a centerpoint of the first diffusioncontact is separated from the lengthwise centerline of the first gateconductive structure by one-half of the first distance as measured inthe second direction.
 5. The semiconductor device as recited in claim 4,wherein a centerpoint of the second diffusion contact is separated fromthe lengthwise centerline of the first gate conductive structure byone-half of the first distance as measured in the second direction; andwherein the centerpoint of the second diffusion contact is separatedfrom the lengthwise centerline of the second gate conductive structureby one-half of the first distance as measured in the second direction.6. The semiconductor device as recited in claim 5, wherein a centerpointof the third diffusion contact is separated from the lengthwisecenterline of the second gate conductive structure by one-half of thefirst distance as measured in the second direction.
 7. The semiconductordevice as recited in claim 6, further comprising: a fourth interconnectconductive structure defined in the interconnect level of thesemiconductor device, the fourth interconnect conductive structurehaving a linear-shape and a lengthwise centerline oriented in the firstdirection, the lengthwise centerline of the fourth interconnectconductive structure separated from the lengthwise centerline of thefirst interconnect conductive structure by one-half of the firstdistance as measured in the second direction, the lengthwise centerlineof the fourth interconnect conductive structure separated from thelengthwise centerline of the second interconnect conductive structure byone-half of the first distance as measured in the second direction. 8.The semiconductor device as recited in claim 7, the fourth interconnectconductive structure having a width measured in the second directionthat is at least twice the width of the first gate conductive structureas measured in the second direction.
 9. The semiconductor device asrecited in claim 7, wherein the lengthwise centerline of the fourthinterconnect conductive structure is co-aligned with the lengthwisecenterline of the first gate conductive structure.
 10. The semiconductordevice as recited in claim 9, further comprising: a first gate contactextending between the first gate conductive structure and the fourthinterconnect conductive structure.
 11. The semiconductor device asrecited in claim 10, wherein the first gate contact is substantiallycentered in the second direction on the first gate conductive structure.12. The semiconductor device as recited in claim 11, wherein the fourthinterconnect conductive structure is positioned to overlap an end of thefirst gate conductive structure in the first direction.
 13. Thesemiconductor device as recited in claim 11, wherein the fourthinterconnect conductive structure is separated from the firstinterconnect conductive structure by an interconnect level end-to-endspacing as measured in the first direction.
 14. The semiconductor deviceas recited in claim 11, further comprising: a third gate conductivestructure defined in the gate level of the semiconductor device, thethird gate conductive structure having a lengthwise centerline orientedin the first direction, the lengthwise centerline of the third gateconductive structure co-aligned with the lengthwise centerline of thefirst gate conductive structure; a fourth gate conductive structuredefined in the gate level of the semiconductor device, the fourth gateconductive structure having a lengthwise centerline oriented in thefirst direction, the lengthwise centerline of the fourth gate conductivestructure co-aligned with the lengthwise centerline of the second gateconductive structure; a fourth diffusion region positioned along aportion of a first side of the third gate conductive structure; a fifthdiffusion region positioned along a portion of a second side of thethird gate conductive structure, the fifth diffusion region alsopositioned along a portion of a first side of the fourth gate conductivestructure, wherein the third gate conductive structure and the fourthdiffusion region and the fifth diffusion region together form a thirdtransistor; and a sixth diffusion region positioned along a portion of asecond side of the fourth gate conductive structure, wherein the fourthgate conductive structure and the fifth diffusion region and the sixthdiffusion region together form a fourth transistor.
 15. Thesemiconductor device as recited in claim 14, wherein the third gateconductive structure is separated from the first gate conductivestructure by a gate level end-to-end spacing as measured in the firstdirection; and wherein the fourth gate conductive structure is separatedfrom the second gate conductive structure by the gate level end-to-endspacing as measured in the first direction.
 16. The semiconductor deviceas recited in claim 14, wherein each of the fourth diffusion region, andthe fifth diffusion region, and the sixth diffusion region has asubstantially equal size as measured in the first direction.
 17. Thesemiconductor device as recited in claim 14, further comprising: a fifthinterconnect conductive structure defined in the interconnect level ofthe semiconductor device, the fifth interconnect conductive structurehaving a linear-shape and a lengthwise centerline oriented in the firstdirection, the lengthwise centerline of the fifth interconnectconductive structure co-aligned with the lengthwise centerline of thefirst interconnect conductive structure; a sixth interconnect conductivestructure defined in the interconnect level of the semiconductor device,the sixth interconnect conductive structure having a linear-shape and alengthwise centerline oriented in the first direction, the lengthwisecenterline of the sixth interconnect conductive co-aligned with thelengthwise centerline of the second interconnect conductive structure;and a seventh interconnect conductive structure defined in theinterconnect level of the semiconductor device, the seventh interconnectconductive structure having a linear-shape and a lengthwise centerlineoriented in the first direction, the lengthwise centerline of theseventh interconnect conductive structure co-aligned with the lengthwisecenterline of the third interconnect conductive structure.
 18. Thesemiconductor device as recited in claim 17, wherein the fifthinterconnect conductive structure has a width measured in the seconddirection that is substantially equal to the width of the firstinterconnect conductive structure, and wherein the sixth interconnectconductive structure has a width measured in the second direction thatis substantially equal to the width of the second interconnectconductive structure, and wherein the seventh interconnect conductivestructure has a width measured in the second direction that issubstantially equal to the width of the third interconnect conductivestructure.
 19. The semiconductor device as recited in claim 17, furthercomprising: an eighth interconnect conductive structure defined in theinterconnect level of the semiconductor device, the eighth interconnectconductive structure having a linear-shape and a lengthwise centerlineoriented in the first direction, the lengthwise centerline of the eighthinterconnect conductive structure co-aligned with the lengthwisecenterline of the second gate conductive structure; and a second gatecontact extending between the fourth gate conductive structure and theeighth interconnect conductive structure, the second gate contactsubstantially centered in the second direction on the fourth gateconductive structure.
 20. A method for fabricating a semiconductordevice, comprising: forming a first gate conductive structure in a gatelevel of the semiconductor device, the first gate conductive structurehaving a linear-shape and a lengthwise centerline oriented in a firstdirection parallel to a substrate of the semiconductor device; forming asecond gate conductive structure in the gate level of the semiconductordevice, the second gate conductive structure having a linear-shape and alengthwise centerline oriented in the first direction, the lengthwisecenterline of the second gate conductive structure separated from thelengthwise centerline of the first gate conductive structure by a firstdistance as measured in a second direction, the second directionoriented perpendicular to the first direction and parallel to thesubstrate of the semiconductor device; forming a first diffusion regionalong a portion of a first side of the first gate conductive structure;forming a second diffusion region along a portion of a second side ofthe first gate conductive structure, the second diffusion region alsopositioned along a portion of a first side of the second gate conductivestructure, wherein the first gate conductive structure and the firstdiffusion region and the second diffusion region together form a firsttransistor; forming a third diffusion region along a portion of a secondside of the third gate conductive structure, wherein the second gateconductive structure and the second diffusion region and the thirddiffusion region together form a second transistor; forming a firstinterconnect conductive structure in an interconnect level of thesemiconductor device, the interconnect level of the semiconductor deviceformed above the gate level of the semiconductor device, the firstinterconnect conductive structure having a linear-shape and a lengthwisecenterline oriented in the first direction, the lengthwise centerline ofthe first interconnect conductive structure separated from thelengthwise centerline of the first gate conductive structure by one-halfof the first distance as measured in the second direction, the firstinterconnect conductive structure having a width measured in the seconddirection that is at least twice a width of the first gate conductivestructure as measured in the second direction; forming a secondinterconnect conductive structure in the interconnect level of thesemiconductor device, the second interconnect conductive structurehaving a linear-shape and a lengthwise centerline oriented in the firstdirection, the lengthwise centerline of the second interconnectconductive structure separated from the lengthwise centerline of thefirst gate conductive structure by one-half of the first distance asmeasured in the second direction, the lengthwise centerline of thesecond interconnect conductive structure separated from the lengthwisecenterline of the third gate conductive structure by one-half of thefirst distance as measured in the second direction, the secondinterconnect conductive structure having a width measured in the seconddirection that is at least twice the width of the first gate conductivestructure as measured in the second direction; and forming a thirdinterconnect conductive structure in the interconnect level of thesemiconductor device, the third interconnect conductive structure havinga linear-shape and a lengthwise centerline oriented in the firstdirection, the lengthwise centerline of the third interconnectconductive structure separated from the lengthwise centerline of thesecond gate conductive structure by one-half of the first distance asmeasured in the second direction, the third interconnect conductivestructure having a width measured in the second direction that is atleast twice the width of the first gate conductive structure as measuredin the second direction.